Compute Express Link

Compute Express Link (CXL) is an open standard for high-speed central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers.[1][2][3][4] CXL is built on the PCI Express (PCIe) physical and electrical interface with protocols in three areas: input/output (I/O), memory, and cache coherence.

Compute Express Link
Year created2019 (2019)
SpeedFull duplex
1.x, 2.x (32 GT/s):
  • 3.938 GB/s (×1)
  • 63.01 GB/s (×16)
Websitewww.computeexpresslink.org

History

Founding members were Alibaba Group, Cisco Systems, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, Intel Corporation and Microsoft.[5] Since then, many others were listed on their web site.

On April 2, 2019, Intel announced their family of Agilex FPGAs featuring CXL.[6] On May 11, 2021, Samsung announced a DDR5 based memory expansion module that allows for terabyte level memory expansion along with high performance for use in data centres and potentially next generation PCs. [7]

On April 2, 2020, the Compute Express Link and Gen-Z Consortiums announced their execution of a memorandum of understanding (MoU), describing a mutual plan for collaboration between the two organizations.[8][9] In November 2021 the CXL Consortium and the GenZ Consortium signed a letter of intent for Gen-Z to transfer its specifications and assets to CXL, leaving CXL as the sole industry standard moving forward.[10]

Specifications released include the following.

CXL Specification 1.0

On March 11, 2019, the CXL Specification 1.0 based on PCIe 5.0 was released. The founding promoter members of the CXL specification included: Alibaba Group, Cisco Systems, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, Intel, and Microsoft.[11]

CXL Specification 1.1

In June, 2019, the CXL Specification 1.1 was released.

On July 18, 2019, Advanced Micro Devices (AMD) joined CXL.[12]

CXL Specification 2.0

On November 10, 2020, the CXL Specification 2.0 was released. There is no bandwidth increase from CXL 1.x, because CXL 2.0 still utilizes PCIe 5.0.

See also

References
  1. "ABOUT CXL". Compute Express Link. Retrieved 2019-08-09.
  2. "Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs". finance.yahoo.com. Yahoo! Finance. Retrieved 2019-11-09.
  3. "A Milestone in Moving Data". Intel Newsroom. Intel. Retrieved 2019-11-09.
  4. "Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors". www.businesswire.com. Business Wire. 2019-09-17. Retrieved 2019-11-09.
  5. "Compute Express Link: Our Members". CXL Consortium. 2020. Retrieved 2020-09-25.
  6. "How do the new Intel Agilex FPGA family and the CXL coherent interconnect fabric intersect?". PSG@Intel. 2019-05-03. Retrieved 2019-08-09.
  7. "Samsung Unveils Industry-First Memory Module Incorporating New CXL Interconnect Standard". Samsung. 2021-05-11. Retrieved 2021-05-11.
  8. "CXL Consortium and Gen-Z Consortium Announce MOU Agreement" (PDF). Beaverton, Oregon. April 2, 2020. Retrieved September 25, 2020.
  9. "CXL Consortium and Gen-Z Consortium Announce MOU Agreement". April 2, 2020. Retrieved April 11, 2020.
  10. CXL Consortium statement, 10 November 2021
  11. Cutress, Ian. "CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel". Anandtech. Retrieved 2019-08-09.
  12. Papermaster, Mark (July 18, 2019). "AMD Joins Consortia to Advance CXL, a New High-Speed Interconnect for Breakthrough Performance". Community.AMD. Retrieved 2020-09-25.
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